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中南大学学报(英文版)

Journal of Central South University

Vol. 26    No. 12    December 2019

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A reconfigurable computing architecture for 5G communication
GUO Yang(郭阳)1, 2, LIU Zi-Jun(刘子君)1, YANG Lei(杨磊)1, LI Huan(李桓)1, WANG Dong-lin(王东琳)1

1. Institute of Automation, Chinese Academy of Sciences, Beijing 100190, China;
2. University of Chinese Academy of Sciences, Beijing 100049, China

Abstract:5G baseband signal processing places greater real-time and reliability requirements on hardware. Based on the architecture of the MaPU, a reconfigurable computing architecture is proposed according to the characteristics of the 5G baseband signal processing. A dedicated instruction set for 5G baseband signal processing is proposed. The corresponding functional units are designed for reuse of hardware resources. A redirected register file is proposed to address latency and power consumption issues in internetwork. A two-dimensional code compression scheme is proposed for cases in which the use ratio of instruction memory is low. The access mode of the data memory is extended, the performance is improved and the power consumption is reduced. The throughput of 5G baseband processing algorithm is one to two orders of magnitude higher than that of the TMS320C6670 with less power consumption. The silicon area evaluated by layout is 5.8 mm2, which is 1/6 of the MaPU’s. The average power consumption is 0.7 W, which is 1/5 of the MaPU’s.

 

Key words: 5G communication; instruction set; register file; code compression; throughput; power consumption

中南大学学报(自然科学版)
  ISSN 1672-7207
CN 43-1426/N
ZDXZAC
中南大学学报(英文版)
  ISSN 2095-2899
CN 43-1516/TB
JCSTFT
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